Typically, the analog front end of a high-speed receiver uses a high-speed slicer circuit that is composed of a front-end master latch and subsequent slave latches. To enable high receiver performance, the high-speed slicer must have high sensitivity to low amplitude input signals.
FIG. 1 is a schematic illustration of a typical master latch 100 for a high-speed slicer circuit. The master latch 100 includes a differential pair of input sampling transistors 112 and 114, a pair of latch transistors 113 and 115, and a transistor 110 configured as a constant current source. The current source 110 can be alternately coupled to the sources of the sampling transistors 112 and 114 through a coupling transistor 116 or to the sources of the latch transistors 113 and 115 through a coupling transistor 117. The drain of sampling transistor 112 is coupled to a power supply through a resistor 105 and an inductor 103, while the drain of sampling transistor 114 is coupled to the power supply through a resistor 106 and an inductor 104. Latch transistors 113 and 115 latch the voltage appearing across the drains of sampling transistors 112 and 114 at points 107 and 108, respectively. Output 107 is cross-coupled to the drain of latch transistor 113 and the gate of latch transistor 115, while output 108 is cross-coupled to the drain of latch transistor 115 and the gate of latch transistor 113.
In operation, the master latch 100 is driven by a pair of clocks 120 and 121 that are 180 degrees out of phase. During a positive phase of clock 120 (negative phase of clock 121), transistor 116 couples current source 110 to the sources of the sampling transistors 112 and 114, while transistor 117 decouples current source 110 from the sources of the latch transistors 113 and 115. Similarly, during a negative phase of clock 120 (positive phase of clock 121), coupling transistor 116 decouples current source 110 from the sources of the sampling transistors 112 and 114, while coupling transistor 117 couples current source 110 to the sources of the latch transistors 113 and 115. Thus, sampling transistors 112 and 114 are sensitive to a pair of differential input signals 101 and 102 only during positive phases of clock 120. When one or both of sampling transistors 112 and 114 are turned on by respective input signals 101 and 102, the total current flowing through either or both transistors is a constant that is determined by the size of current source 110. When input signal 101 is larger than input signal 102, more current flows through transistor 112 than through transistor 114, and the voltage drop across resistor 105 is larger than the voltage drop across resistor 106. As a result, the output voltage across the drain of transistor 114 at point 108 is larger than the output voltage across the drain of transistor 112 at point 107. Conversely, when input signal 101 is smaller than input signal 102, less current flows through transistor 112 than through transistor 114, and the voltage drop across resistor 105 is smaller than the voltage drop across resistor 106. As a result, the output voltage across the drain of transistor 114 at point 108 is smaller than the output voltage across the drain of transistor 112 at point 107. During negative phases of clock 120 (and therefore positive phases of clock 121), latch transistors 113 and 115 latch the output voltages appearing across the drains of sampling transistors 112 and 114 at points 107 and 108, respectively.